Magnetic Frontiers – Spintronics for Computing

This conference will convene researchers across materials, devices, circuits, EDA, architecture, and applications to define metrics, surface integration barriers, and chart roadmaps for computing‑class spintronics. Both fundamental advances and applied developments will be covered, with strong participation from industry and early‑career researchers. The program emphasizes end‑to‑end co‑design—from materials stacks and device physics through compact models and PDKs to array‑level demonstrations, benchmarks, and system prototypes— along with reliability, manufacturability, and standards needed for industrial uptake. Poster sessions, tutorials, and panel discussions will foster deep interaction and consensus on figures of merit relevant to computing (e.g., array‑level energy–delay, accuracy–energy trade‑offs, retention/endurance under compute workloads).

With technical sponsorship from IEEE, this event anticipates that its proceedings will be indexed in leading databases such as Scopus, Web of Science (WoS), Ei Compendex, DBLP, and Google Scholar.